System having one or more memory devices

ABSTRACT

A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/033,577, filed on Feb. 19, 2008, which claims the benefit of priorityof U.S. Provisional Patent Application No. 60/902,003 filed on Feb. 16,2007, and U.S. Provisional Patent Application Ser. No. 60/892,705 filedon Mar. 2, 2007, the contents of which are incorporated herein byreference in their entirety.

BACKGROUND

Flash memory is a commonly used type of non-volatile memory inwidespread use as mass storage for consumer electronics, such as digitalcameras and portable digital music players for example. The density of apresently available Flash memory component, consisting of 2 stackeddies, can be up to 32 Gbits (4 GB), which is suitable for use in popularUSB Flash drives, since the size of one Flash component is typicallysmall.

The advent of 8 mega pixel digital cameras and portable digitalentertainment devices with music and video capabilities has spurreddemand for ultra-high capacities to store the large amounts of data,which may not be met by the single Flash memory device. Therefore,multiple Flash memory devices are combined together into a system toeffectively increase the available storage capacity. For example, Flashstorage densities of 20 GB may be required for such applications.

FIG. 1 is a block diagram of a prior art system 10 integrated with ahost system 12. The prior art system 10 includes a memory controller 14in communication with host system 12, and multiple non-volatile memorydevices 16. The host system 12 includes a processing device such as amicrocontroller, microprocessor, or a computer system. The prior artsystem 10 of FIG. 1 is organized to include one channel 18, with thememory devices 16 being connected in parallel to channel 18. Thoseskilled in the art should understand that the prior art system 10 canhave more or fewer than four memory devices connected to it.

Channel 18 includes a set of common buses, which include data andcontrol lines that are connected to all of its corresponding memorydevices. Each memory device is enabled or disabled with respective chipselect (enable) signals CE1#, CE2#, CE3# and CE4#, provided by memorycontroller 14. The “#” indicates that the signal is an active low logiclevel signal. At most one of the chip select signals is typicallyselected at one time. The memory controller 14 is responsible forissuing commands and data, via the channel 18, to a selected memorydevice in response to the operation of the host system 12. Read dataoutput from the memory devices is transferred via the channel 18 back tothe memory controller 14 and host system 12. Operation of the prior artsystem 10 can be asynchronous or synchronous. FIG. 1 illustrates anexample of a synchronous system that uses a clock (CK), which isprovided in parallel to each memory device 16 to synchronize datatransfer on the channel 18. The prior art system 10 is generally said toinclude a multi-drop bus, in which the memory devices 16 are connectedin parallel with respect to channel 18.

In the prior art system 10, non-volatile memory devices 16 may be (butnot necessarily) substantially identical to each other, and aretypically NAND flash memory devices. Those skilled in the art shouldunderstand that flash memory may be organized into banks, and that eachbank may be organized into blocks to facilitate block erasure. Somecommercially available NAND flash memory devices have two banks ofmemory.

There are specific issues that can adversely impact performance of thesystem. The structure of the prior art system 10 imposes physicalperformance limitations. There is a large number of parallel signalsextending across the system, and the signal integrity of the signalsthey carry may be degraded by crosstalk, signal skew, and simultaneousswitching noise (SSN). Input/output power consumption in such a systembecomes an issue as each signal track between the flash controller andflash memory devices is frequently charged and discharged for signaling.With increasing system clock frequencies, the power consumption willincrease.

There is also a practical limit to the number of memory devices whichcan be connected in parallel to the channel since the drive capabilityof a single memory device is small relative to the loading of the longsignal tracks. Furthermore, as the number of memory devices increase,more chip enable signals (CE#) are required, and CK may need to berouted to the additional memory devices, all of which are longer as theyare routed to the memory devices. Clock performance issues due toextensive clock distribution are well known in the art, become an issuein large Prior Art systems with many memory devices 16. Therefore, for aPrior Art memory system to include a large number of memory devices,either the memory devices are spread across multiple channels or thefrequency operation of the memory system would be limited; either optioninvolves compromises. A controller having multiple channels andadditional chip enable signals increases the cost of the system.Otherwise, the system is limited to a small number of memory devices.

In the multi-drop prior art system 10 of FIG. 1, the data width of eachmemory device 16 must be the same. For example, if the data channelwidth is 32 bits then each memory device 16 must be a x32 device. If analternate multi-drop system has an 8 bit data channel width, then thex32 memory devices cannot be used. Instead, different x8 memory devicesneed to be used instead. Accordingly, a memory device manufacturer willproduce versions of the same memory device with different data widths inorder to accommodate the possible system structures.

As consumer demand for smaller form factor products increases,manufacturers need to find ways to minimize the area or space occupiedby semiconductor chips, such as the prior art system 10 of FIG. 1.Although each memory device chip can be small, the package encapsulatingthe chip may have a size largely determined by the number of packagepins for coupling signals between the chip input/output pads and theprinted circuit board (PCB) traces. Unfortunately, the prior art system10 of FIG. 1 is not suited for applications requiring a minimized PCBarea. Each memory device and the memory controller will occupy a largerPCB area due to x8, x16 or even x32 data channel widths because thepackage size increases as the data width increases. If the data width isreduced to minimize the package size, then performance is adverselyimpacted since the aggregate memory system peak bandwidth is reduced.

It is, therefore, desirable to provide a high performance system whichconsumes a minimal amount of board area.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 is a block diagram of a prior art system comprising Flashdevices;

FIG. 2A is a block diagram of a system receiving a parallel clocksignal;

FIG. 2B is a block diagram of a system receiving a source synchronousclock signal in series;

FIG. 3A is a detailed block diagram of the system of FIG. 2B;

FIG. 3B is a detailed block diagram of the system of FIG. 2A;

FIG. 4 is a block diagram of a generic memory device having a core andan input/output interface for use in the systems of FIGS. 3A and 3B;

FIG. 5A is an example illustration of a memory device interconnected toa PCB through a package;

FIG. 5B is an example illustration of a system in package deviceincluding serially connected memory dies;

FIG. 6 is a block diagram of a memory device embodiment havingconfigurable data widths;

FIG. 7 is a block diagram of a dynamically adjustable system embodiment;

FIG. 8A is a flow chart of a method for setting an active data width ofa system, according to a presently described embodiment;

FIG. 8B is an illustration of an example system having configurable datawidths;

FIG. 9 is an illustration of a modular command packet structure for thesystems of FIGS. 3A and 3B;

FIG. 10 shows a table listing example modular command packets foroperating the systems of FIGS. 3A and 3B;

FIG. 11 is a circuit schematic embodiment of device address logic in amemory device of the systems of FIGS. 3A and 3B;

FIG. 12 is a circuit schematic embodiment of the broadcast addressdetector shown in FIG. 11;

FIG. 13 is an alternate circuit schematic embodiment of the broadcastaddress detector shown in FIG. 11;

FIG. 14 is a flow chart of a method for executing a broadcast operationin the systems of FIGS. 3A and 3B, according to a presently describedembodiment;

FIG. 15 is a sequence diagram illustrating an example valid readoperation for the systems of FIGS. 3A and 3B, according to a presentlydescribed embodiment;

FIG. 16 is a sequence diagram illustrating an example valid readoperation for the systems of FIGS. 3A and 3B, according to a presentlydescribed embodiment;

FIG. 17 is a circuit schematic embodiment of data output control logicand data output circuits of the memory device shown in FIG. 6;

FIG. 18 is a sequence diagram illustrating an example invalid readoperation;

FIG. 19 is a sequence diagram illustrating another example invalid readoperation;

FIG. 20 is a sequence diagram illustrating another example invalid readoperation; and,

FIG. 21 is a flow chart of a data output inhibit algorithm, according toa presently described embodiment.

DETAILED DESCRIPTION

In a first aspect, there is provided a system having a memory controllerand a memory device. The memory controller includes a first number ofoutput ports, the memory controller providing a command to accessmaximum data width configuration data from one output port of the firstnumber of output ports. The memory device includes an input/outputregister for storing the maximum data width configuration data, a secondnumber of data input pads and the second number of data output pads. Thememory device receives the command at one data input pad of the secondnumber of data input pads, and provides the maximum data widthconfiguration data from one data output pad of the second number of dataoutput pads. According to embodiments of the present aspect, the maximumdata width configuration data is hardwired in the input/output register,and the memory controller includes the first number of input ports forreceiving the maximum data width configuration data from one input portof the first number of input ports. In another embodiment, all of thesecond number of data input pads are disabled except for the one datainput pad, and all of the second number of data output pads are disabledexcept for the one data output pad.

In an aspect of the embodiment, the memory device includes a currentactive width register for storing a configuration code received from thememory controller. The configuration code enables a third number of thedata input pads and the third number of the data output pads, where thethird number is less than or equal to the second number. Furthermore,the memory device includes a memory die encapsulated in a package, wherethe package has a fourth number of data input pins and data output pins.In this embodiment, a smallest common number of data input pins areelectrically connected to the smallest common number of data input pads,where the smallest common number is the smaller of the second number andthe fourth number. The third number can be between one and the smallestcommon number. In a further aspect of the embodiment, there is provideda fifth number of conductive tracks electrically connecting the firstnumber of output ports to the fourth number of input pins, and the thirdnumber is the smaller of the smallest common number and the fifth numberof conductive tracks.

In a second aspect, there is provided a memory device having a currentactive width register, a first data input/output circuit block and asecond data input/output circuit block. The current active widthregister stores a configuration code. The first data input/outputcircuit block receives the configuration code from a data input pad. Thedata input/output circuit block passes the configuration code to thecurrent active width register. The second data input/output circuitblock is selectively enabled in response to the configuration codestored in the current active width register. In an embodiment of thepresent aspect, there is further provided an input/output register forstoring maximum data width configuration data, where the maximum datawidth configuration data is provided by the first data input/outputcircuit block through a data output pad. In a further aspect of thecurrent embodiment, the current active width register, the first datainput/output circuit block, the second data input/output circuit block,the input/output register, the data input pad and the data output padare formed on a memory die encapsulated in a package. The package caninclude exactly one data input pin coupled to the first datainput/output circuit block. Alternately, the package can include a firstdata input pin coupled to the first data input/output circuit block, anda second data input pin coupled to the second data input/output circuitblock. Furthermore, the package can include at least one more additionaldata input pin.

In a third aspect, there is provided a method for setting a data widthfor a system having at least one memory device connected in a ringtopology configuration with a memory controller. The method includesaccessing configuration data stored in the at least one memory device,the configuration data corresponding to a maximum data width of the atleast one memory device; determining a smallest data width of all theconfiguration data; and setting a selected data width between one andthe smallest data width in the at least one memory device. According toembodiments of the present aspect, accessing can include assigning anidentification number for the at least one memory device, and issuing aread command serially on a single data line corresponding to a datawidth of one. In an aspect of the embodiment, the selected data width isdetermined by an operating profile of the system, where the operatingprofile corresponds to maximizing performance of the system by settingthe selected data width to be the smallest data width. Alternately, theoperating profile corresponds to minimizing power consumption of thesystem by setting the selected data width to be one.

In a further embodiment of the present aspect, setting includes loadinga current active width register of the at least one memory device with aconfiguration code corresponding to the selected data width. Setting canfurther include issuing a command addressed to the at least one memorydevice for writing the configuration code to the current active widthregister. In another embodiment, the system includes a plurality ofmemory devices connected in series, and setting includes issuing acommand with a broadcast address recognizable by the plurality of memorydevices for writing the configuration code to the current active widthregister of each of the plurality of memory devices.

In a fourth aspect, there is provided a method for broadcasting acommand to memory devices serially connected in a ring topologyconfiguration with a memory controller. The method includes issuing onecommand packet having an op code corresponding to the command, and abroadcast address; receiving the command packet serially in the memorydevices, each of the memory devices being configured to recognize anassigned device address and the broadcast address; executing the op codein each of the memory devices in response to the broadcast address; andpassing the command packet from a last memory device of the memorydevices to the memory controller to end broadcasting. In an embodimentof the present aspect, the command packet includes an address fieldn-bits in length for providing 2̂n total device addresses, where (2̂n)−1of the total device addresses are assigned device addresses and one ofthe (2̂n)−1 total device addresses is the broadcast address. Thebroadcast address can be a highest logical address of the 2̂n totaldevice addresses, where each of the memory devices logically decodes thebroadcast address for enabling execution of the op code. Alternately, anassigned broadcast address is stored in each of the memory devices suchthat the broadcast address is matched to the assigned broadcast addressfor enabling execution of the op code.

In a fifth aspect, there is provided a method for inhibiting data outputin a memory device. The method includes receiving a data output controlsignal for outputting read data; and inhibiting data output circuitswhen a previously received command corresponds to a non-read relatedcommand, and enabling the data output circuits when the previouslyreceived command corresponds to a read-related command. In an embodimentof the present aspect, inhibiting includes outputting a continuoussequence of data corresponding to one of logic “1” data and logic “0”data. Enabling includes operating a serial data register to provide theread data serially in response to a clock while the data output controlsignal is at an active logic level. Inhibiting includes de-coupling theclock from the serial data register while the data output control signalis at the active logic level. In the present embodiment, the previouslyreceived command is latched in response to a command latch signal at anactive logic level, and the clock is logically de-coupled from theserial data register when a control signal corresponding to a writeoperation is latched in response to the active logic level of thecommand latch signal.

In a sixth aspect, there is provided a read data output circuitincluding a serial data register, first logic circuitry and second logiccircuitry. The serial data register serially outputs read data inresponse to a clock. The first logic circuitry couples the clock to theserial data register in response to an active logic level of a dataoutput control signal. The second logic circuitry disables the clockduring a non-read related operation.

A system that resolves many performance issues of the prior art system10 of FIG. 1 is a system in which the memory devices are seriallyconnected with each other and the memory controller in a ring topologyconfiguration. FIGS. 2A and 2B are block diagrams illustrating theconceptual nature of a system according to the presently describedembodiments. FIG. 2A is a block diagram of a system receiving a parallelclock signal while FIG. 2B is a block diagram of the same system of FIG.2A receiving a source synchronous clock signal. The clock signal can beeither a single ended clock signal or a differential clock pair.

In FIG. 2A, the system 20 includes a memory controller 22 having atleast one output port Sout and an input port Sin, and memory devices 24,26, 28 and 30 that are connected in series. While not shown in FIG. 2A,each memory device has an Sin input port and an Sout output port. Inputand output ports consist of one or more physical pins or connectionsinterfacing the memory device to the system it is a part of. In oneembodiment, the memory devices can be flash memory devices. Alternately,the memory devices can be DRAM, SRAM or any other type of memory deviceprovided it has an input/output interface compatible with a specificcommand structure, for executing commands or for passing throughcommands and data to the next memory device. The current example of FIG.2A includes four memory devices, but alternate embodiments can include asingle memory device, or any suitable number of memory devices.Accordingly, if memory device 24 is the first device of the system 20 asit is connected to Sout, then memory device 30 is the Nth or last deviceas it is connected to Sin, where N is an integer number greater thanzero. Memory devices 26 to 28 are then intervening serially connectedmemory devices between the first and last memory devices. Each memorydevice can assume a distinct identification (ID) number, or deviceaddress (DA) upon power up initialization of the system, so that theyare individually addressable. Commonly owned U.S. patent applicationSer. No. 11/622,828 titled “APPARATUS AND METHOD FOR PRODUCING IDS FORINTERCONNECTED DEVICES OF MIXED TYPE”, U.S. patent application Ser. No.11/750,649 titled “APPARATUS AND METHOD FOR ESTABLISHING DEVICEIDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES”, U.S. patentapplication Ser. No. 11/692,452 titled “APPARATUS AND METHOD FORPRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OFMIXED TYPE”, U.S. patent application Ser. No. 11/692,446 titled“APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXEDDEVICE TYPE IN A SERIAL INTERCONNECTION”, U.S. patent application Ser.No. 11/692,326 titled “APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPEOF SERIALLY INTERCONNECTED DEVICES”, U.S. patent application Ser. No.11/771,023 titled “ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLYINTERCONNECTED MEMORY DEVICES OF MIXED TYPE” and U.S. patent applicationSer. No. 11/771,241 titled “SYSTEM AND METHOD OF OPERATING MEMORYDEVICES OF MIXED TYPE” describe methods for generating and assigningdevice addresses for serially connected memory devices of a system, thecontents of which are incorporated by reference in their entirety.

Memory devices 24 to 30 are considered serially connected because thedata input of one memory device is connected to the data output of aprevious memory device, thereby forming a series-connection systemorganization, with the exception of the first and last memory devices inthe chain. The channel of memory controller 22 includes data, address,and control information provided by separate pins, or the same pins,connected to conductive lines. The embodiment of FIG. 2A includes onechannel, where the one channel includes Sout and corresponding Sinports. However, memory controller 22 can include any suitable number ofchannels for accommodating separate memory device chains. In the exampleof FIG. 2A, the memory controller 22 provides a clock signal CK, whichis connected in parallel to all the memory devices.

In general operation, the memory controller 22 issues a command throughits Sout port, which includes an operation code (op code), a deviceaddress, optional address information for reading or programming, anddata for programming. The command may be issued as a serial bitstreamcommand packet, where the packet can be logically subdivided intosegments of a predetermined size. Each segment can be one byte in sizefor example. A bitstream is a sequence or series of bits provided overtime. The command is received by the first memory device 24, whichcompares the device address to its assigned address. If the addressesmatch, then memory device 24 executes the command. The command is passedthrough its own output port Sout to the next memory device 26, where thesame procedure is repeated. Eventually, the memory device having thematching device address, referred to as a selected memory device, willperform the operation specified by the command. If the command is a readdata command, the selected memory device will output the read datathrough its output port Sout (not shown), which is serially passedthrough intervening memory devices until it reaches the Sin port of thememory controller 22. Since the commands and data are provided in aserial bitstream, the clock is used by each memory device for clockingin/out the serial bits and for synchronizing internal memory deviceoperations. This clock is used by all the memory devices in the system20.

Because the clock frequency used in the system according FIG. 2A isrelatively low, unterminated full swing CMOS signaling levels can beused to provide robust data communication. This is also referred to asLVTTL signaling, as would be well known to those skilled in the art.

A further performance improvement over the system 20 of FIG. 2A can beobtained by the system of FIG. 2B. System 40 of FIG. 2B is similar tothe system 20 of FIG. 2A, except that the clock signal CK is providedserially to each memory device from an alternate memory controller 42that provides the source synchronous clock signal CK. Each memory device44, 46, 48 and 50 may receive the source synchronous clock on its clockinput port and forward it via its clock output port to the next devicein the system. In some examples of the system 40, the clock signal CK ispassed from one memory device to another via short signal lines.Therefore none of the clock performance issues related to the parallelclock distribution scheme are present, and CK can operate at highfrequencies. Accordingly, the system 40 can operate with greater speedthan the system 20 of FIG. 2A. For example, high speed transceiver logic(HSTL) signaling can be used to provide high performance datacommunication. In the HSTL signaling format, each memory device mayreceive a reference voltage that is used for determining a logic stateof the incoming data signals. Another similar signaling format is theSSTL signaling format. Accordingly, the data and clock input circuits inthe memory devices of the systems 20 and 40 are structured differentlyfrom each other. Both the HSTL and SSTL signaling formats should be wellknown to those skilled in the art.

FIGS. 3A and 3B are block diagrams of systems, where the memory devicesof the system of FIG. 3A receive the clock in parallel and the memorydevices of the system of FIG. 3B receive the clock in series. In thepresently described embodiments, both systems are systems having memorydevices connected in series with each other in a ring topology with thememory controller. Each memory device is designed to receive commandsand data in one or more serial bitstreams received from the memorycontroller or a prior memory device. Generally, commands and read dataflow serially through each memory device in the system. Accordingly,such memory devices can be referred to as serial memory devices sincetheir input and output interface circuits receive and provide dataserially. In the system embodiments of FIGS. 3A and 3B, four memorydevices are shown connected in series in a ring topology with the memorycontroller, however any suitable number of memory devices can beincluded in either system.

In FIG. 3A, the system 100 includes a memory controller 102 and fourmemory devices 104, 106, 108 and 110. The memory controller 102 providescontrol signals in parallel to the memory devices. These include thechip enable signal CE# and the reset signal RST#. In one example use ofCE#, the devices are enabled when CE# is at the low logic level. Inpreviously considered devices, once a Flash memory device started aprogram or erase operation, CE# could be de-asserted, or driven to ahigh logic level. However in the present embodiment, de-asserting CE#has the effect of disabling communication from Sin to Sout of thedisabled serial memory device. Since the serial memory devices areconnected in a ring, disabling any of the devices breaks communicationaround the ring and the memory controller becomes unable to communicatewith all of the memory devices in the memory system. As a result, CE# isa common signal to all serial memory devices, and is used to put theentire memory into a low power state. In one example use of RST#, thememory device is set to a reset mode when RST# is at the low logiclevel. In the reset mode, the power is allowed to stabilize and thedevice prepares itself for operation by initializing all finite statemachines and resetting any configuration and status registers to theirdefault states. The memory controller 102 includes clock output portsCKO# and CKO for providing complementary clock signals CK and CK#, andclock input ports CKI# and CKI for receiving the complementary clocksignals from the last memory device of the system. Each memory devicemay include a clock synthesizer, such as a DLL or a PLL for generatingphases of the received clocks. Certain phases are used to center theclock edges within the input data valid window internally to ensurereliable operation. Each memory device has clock output ports CKO# andCKO for passing the complementary clock signals to the clock input portsof the next memory device, and clock input ports CKI and CKI# forreceiving the complementary clock signals from either the memorycontroller 102 or a previous memory device. The last memory device 110provides the clock signals back to the memory controller 102.

The channel of memory controller 102 includes data output port Sout,data input port Sin, a command strobe input CSI, a command strobe outputCSO (echo of CSI), data strobe input DSI, and a data strobe output DSO(echo of DSI). Output port Sout and input port Sin can be one bit inwidth, or n bits in width where n is a positive integer, depending onthe characteristics of the memory controller. For example, if n is 1then one byte of data is received after eight data latching edges of theclock. A data latching clock edge can be a rising clock edge for examplein single data rate (SDR) operation, or both rising and falling edges ofthe clock for example in double data rate (DDR) operation. If n is 2then one byte of data is received after four latching edges of theclock. If n is 4 then one byte of data is received after two latchingedges of the clock. The memory device can be statically configured ordynamically configured for any width of Sout and Sin. Hence, in aconfiguration where n is greater than 1, the memory controller providesdata in parallel bitstreams. CSI is used for controlling or enabling thelatching command data appearing on the input port Sin, and has a pulseduration for delimiting the time when a command is present on the datainput port Sin. More specifically, the command data will have a durationmeasured by a number of clock cycles, and the pulse duration of the CSIsignal will have a corresponding duration. DSI is used for enabling theoutput port Sout buffer of a selected memory device to output read data,and has a pulse duration for delimiting read data provided from its dataoutput port Sout so that the memory controller knows when to latch dataon its return from the last memory device.

Since the presently described embodiment of FIG. 3A is intended for highspeed operation, a high speed signaling format, such as the HSTLsignaling format for example, is used. Accordingly, a reference voltageVREF is provided to each memory device which is used by each memorydevice to determine the logic level of the signals received at the Sin,CSI and DSI input ports. The reference voltage VREF may be generated byanother circuit on the printed circuit board, for example, and is set toa predetermined voltage level based on the voltage swing mid-point ofthe HSTL signal.

In use of the embodiment of FIG. 3A, each memory device is positioned ona printed circuit board such that the distance and signal track lengthbetween the Sout output port pins on one device and the Sin input portpins of the next device in the ring is minimized. Alternately, the fourmemory devices can be collected in a system in package module (SIP)which further minimizes signal track lengths. Memory controller 102 andmemory devices 104 to 110 are serially connected to form a ringtopology, meaning that the last memory device 110 provides its outputsback to the memory controller 102. As such, those skilled in the artwill understand that the distance between memory device 110 and memorycontroller 102 is easily minimized.

In FIG. 3B, system 200 includes a memory controller 202 and the memorydevices 204, 206, 208 and 210. The memory controller 202 may be designedto provide similar functionality to that of the memory controller 102illustrated in FIG. 3A, except that the clock signals are provided inparallel, therefore the clock output ports CKO# and CKO of each memorydevice are not present or unconnected. Furthermore, the signaling formatfor the data and the strobe signals is different for the system of FIG.3A as compared with the system of FIG. 3B. For example, the signalingformat for the system of FIG. 3B can be the full swing un-terminatedLVTTL signaling format. The LVTTL signaling used in conjunction with/atlower clock frequencies does not use a reference voltage VREF. Memorydevices for use only in systems of FIG. 3B do not need a VREF input. Ifa VREF input is present, it is because they are also capable ofcommunicating according to a high-speed signaling convention that doesrequire VREF. In such a case VREF is set to a voltage level other thanthe signaling midpoint out of convenience or to indicate that LVTTLsignaling is being used. For example, for such a device, VREF might beset to either VDD or VSS to indicate LVTTL signaling and a networkorganization according the FIG. 3B, as opposed to HSTL signaling and anetwork configuration according to FIG. 3A.

According to an example embodiment, memory devices 104, 106, 108 and 110of FIG. 3A and memory devices 204, 206, 208 and 210 of FIG. 3B can beany type of memory device having an input/output interface designed forserial interconnection with other memory devices. According to thepresently described embodiments, the memory devices of FIGS. 3A and 3Bmay be the same, and are thus operable in both systems as they will haveinput and output buffer circuits which can operate with LVTTL inputsignals or HSTL input signals. Those skilled in the art will understandthat the memory devices can include input and output buffer circuits foroperating with other types of signal formats equivalent to LVTTL or HSTLsignals. While these memory devices can be flash memory devices, theymight also be DRAM, SRAM or any other suitable type of volatile ornon-volatile memory device.

FIG. 4 is a block diagram illustrating the conceptual organization of ageneric memory device having a core and an input/output interfacesuitable for use in the systems of FIGS. 3A and 3B. Memory device 300includes a memory core, which includes memory array banks 302 and 304,and control and I/O circuits 306 for accessing the memory array banks302 and 304. Those skilled in the art will understand that the memoryarray can be organized as a single memory bank or with two or morememory banks. The memory core can be DRAM, SRAM, NAND flash, or NORflash memory based for example. Of course, any suitable emerging memoryand its corresponding control circuits can be used. Accordingly,depending on the type of memory core, circuit block 306 can includeerror correction logic, voltage generators, refresh logic and any othercircuit blocks that are required for executing the operations native tothe memory type.

Typically, memory devices use command decoders for initializing therelevant circuits in response to a received command by assertinginternal control signals. They will also include well known I/Ocircuitry for receiving and latching data, commands and addresses.Unlike the corresponding circuits in conventional Flash memories, thememory devices of the present invention includes a serial interface andcontrol logic block 308. This block receives RST#, CE#, CK#, CK, CSI,DSI and Sin inputs, and provides Sout, CSO, DSO, CKO and CKO# outputs.

The interface and control logic block 308 is responsible for variousfunctions, as discussed in commonly owned U.S. Patent Publication No.20070076479 A1. Example functions of interface and control logic block308 include setting a device identifier number, passing data through tothe next serially connected memory device, and decoding a receivedcommand for executing native operations. This circuit receives commandsserially, including commands specific to controlling or configuring theserial operation of the memory device, in addition to native commandsspecific for controlling core memory circuits, including those forstoring and retrieving information from the memory array. For example,the memory devices of the presently described embodiments respond bothto commands relating to management of the serial link (for examplecommands providing read access to a status register) as well nativecommands relating to the storage and retrieval of information. Thecommand set can be expanded to include features usable by the memorycontroller when the memory devices are serially connected. For example,status register information can be requested to assess the status of thememory device.

The setting of a device identifier (ID) number can be done in severalways. For example, the device ID number can be preset or hardwired ineach memory device, or it can be assigned by the memory controller. Onetechnique is ID number self-assignment, which is disclosed in commonlyowned U.S. patent application Ser. No. 11/613,563 filed Dec. 20, 2006,the disclosure of which is incorporated herein by reference in itsentirety. In ID number self-assignment, a write ID operation isinitiated within a first memory device to cause the device to establishan ID. The first memory device receives a first value by acquiring thestate of its Sin input. The first device then establishes a device IDfrom the first value, which may include placing the first value instorage (e.g., a register) associated with the device. The first devicegenerates a second value from the acquired state of the inputs. Thissecond value can be the first value incremented by one for example. Thefirst memory device outputs the second value from its Sout output to asecond memory device. The second memory device receives the second valueand repeats the aforementioned process to establish its unique ID.

In an alternate device ID number assignment technique, described incommonly owned U.S. patent application Ser. No. 11/843,024, filed onAug. 22, 2007, the contents of which are incorporated by reference, thememory devices of the system are first initialized into a reset state,followed by the memory controller iteratively issuing specific device IDnumbers to each memory device. The first memory device will receive andaccept the assigned ID number, and then exit from the reset state. Inthe reset state, the memory devices will not pass device ID numbers tothe subsequent memory device. The memory controller monitors its datainput for an echo of the assigned ID number. If the echo is not receivedafter a predetermined period of time, then the next ID number is issued.Intervening memory devices not in the reset state will pass the IDnumber to the next memory device.

The systems of FIGS. 3A and 3B can include a mix of memory device types,each providing different advantages for the host system. Such systemshaving memory devices of mixed types is disclosed in commonly owned U.S.Provisional Patent Application No. 60/868,773 filed Dec. 6, 2006, thedisclosure of which is incorporated herein by reference in its entirety.Further details are such systems are disclosed in commonly owned U.S.patent application Ser. No. 11/771,023 titled “ADDRESS ASSIGNMENT ANDTYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXEDTYPE”, and in commonly owned U.S. patent application Ser. No. 11/771,241titled “SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE”,the contents of which are incorporated by reference. For example, thehigh speed of DRAM memory can be use as a cache while non-volatile flashmemory can be used for low power mass data storage. Regardless of thetype of memory device being used, each memory device is individuallyaddressable to act upon a command because the interface and controllogic block 308 receives commands according to a predetermined protocol.Furthermore, non-memory devices can be included in the systems of FIGS.3A and 3B, provided they can act on serially received commands, and passthe commands and read data to subsequent devices in the system.

An advantage of the memory devices shown in FIGS. 3A, 3B and 4, is thata memory device manufactured to be a x8 physical device width, meaningthat it will have Sin[0:7] serial input ports and correspondingSout[0:7] serial output ports, does not have to use all its input andoutput ports. This means that a single x8 serial memory device can beselectively and dynamically configured to be used in a wide variety ofsystems with different effect channel widths. A benefit of thiscapability is that a system designer can choose from a wider selectionof available parts when architecting a new system. The other side ofthis benefit is that memory vendors can sell memory devices that areintrinsically wide into systems that have narrow links.

FIG. 5A is a drawing showing a top down view of a package 400encapsulating a memory die 402 in one possible way. Package 400 with amemory die 402 corresponds to a memory device shown in FIGS. 3A and 3B.The package 400 has data input pins 404, and data output pins 408, whichare structures for electrically connecting the die 402 to a printedcircuit board (PCB) 412. In the PCB 412 includes a link consisting of aset of conductive tracks or traces 406 and 410, which are connected tothe pins 404 and 408 of the package 400. In FIG. 5A, each set of traces406 and 410 includes eight individual traces. The memory die 402 hasdata input pads 414 and corresponding data output pads 418. The datainput pads 414 are electrically connected to corresponding data inputpins 404, and the data output pads 418 are electrically connected tocorresponding data output pins 408. These electrical connections arepresently shown in FIG. 5A as bond wires 416, but solder bumps can beused instead. In the present example, only the data input and outputpads and pins are shown, while the control signal inputs and outputs,and voltage supply inputs are not shown in order to simplify thediagram.

FIG. 5B is a drawing showing a side view of a system in package (SIP)450 encapsulating two memory dies 452 and 454 in one possibleorganization, where the memory dies 452 and 454 are the same as memorydie 402 shown in FIG. 5A. Each memory die has data input pads 414 anddata output pads 418. Also referred to as a multi-chip package, SIP 450has data input pins 456, and data output pins 458. In the present view,only one of the data input pins, data output pins, data input pads anddata output pads are shown. The two memory dies are positionedside-by-side, where memory die 452 has its data input pad 414 connectedto data input pin 456 via bond wire 460 and memory die 454 has its dataoutput pad 418 connected to data output pin 458 via bond wire 462.Memory device 452 has its data output pad 418 connected to the datainput pad 414 of memory device 454 via bond wire 464. In such anorganization, the internal wiring of bond wires 460, 462 and 464 areequivalent to the links 406/410 of the PCB 412. FIG. 5 b shows onepossible internal layout of the memory dies, and those skilled in theart will understand that the dies 452 and 454 can be stacked.

In the present examples of FIGS. 5A and 5B, the memory die has aphysical device width, defined as the number of input data pads andoutput data pads formed on the die. The package width is the number ofinput data pins and output data pins on the package. These pins for theinput port Sin[1:n] and the output port Sout[1:n] of the serial memorydevice that is the union of the package 400 and the memory die 402. Thelink width is the number of conductive tracks formed on the PCB. Thememory die 402 of FIG. 5A has a x4 physical device width, as it ismanufactured for receiving four input data streams through its datainput pads 414 and for providing four corresponding output data streamsthrough its data output pads 418. The package 400 has two input datapins 404 and two corresponding data output pins 408. The link widthtotals eight, but only the top two are connected to the pins of package400. The maximum number of data input pads 414 and data output pads 418of the memory die 402 that are active, or enabled, is physically limitedby the maximum number of data pins 404/408 of the package 400. From thispoint on, reference to data pins or pads of memory die 402 and package400 will include both data input and output pads and pins for the sakeof convenience. Because the bottom two data pads 414/418 of the memorydie 402 are not connected, they are dynamically disabled from use andthe memory die 402 receives and provides data only from its top two datapads 414/418. In use, the bottom two data input pads 414 can be leftopen and the bottom two data output pads 418 can be bonded to a supplyvoltage such as VSS. Therefore for any system which includes thispackage 400, the active width can either be x1 or x2. The maximum activewidth for the present packaging example is x2, where a maximum activewidth refers to the data width of the system. Although memory die 402 ofthe present example is manufactured as a x4 die, the memory die 402 canbe dynamically configured to operate at less than a x4 width. In thepresent example, if the memory die 402 in this package 400 isdynamically configured to operate a x4 width, then it would actuallyreceive only half of the bits it was expecting. The system so configuredwould be non-functional.

Table 1 shows some example combinations of the link width, number ofdata pins on the package, the maximum number of usable data pads for amemory die manufactured with a total of 1, 2, 4 and 8 data pads.

Physical Link Physical Package Memory Die Data Maximum Usable Width DataWidth Port Width Data Path Width 1 1 1 1 4 1, 2, 4 1, 1, 1 8 1, 2, 4, 81, 1, 1, 1 2 1 1 1 4 1, 2, 4 1, 2, 2 8 1, 2, 4, 8 1, 2, 2, 2 4 1 1 1 41, 2, 4 1, 2, 4 8 1, 2, 4, 8 1, 2, 4, 4 8 1 1 1 4 1, 2, 4 1, 2, 4 8 1,2, 4, 8 1, 2, 4, 8

The final column titled “Maximum usuable data path width” illustratesthat for each combination of these characteristics, there is a maximumusable number of data pads for the device in a system. It is the largestinteger that is smaller than or equal to each of the physicalcharacteristics in the first three columns. For example, if the physicallink width connecting this memory device to the next is 2 bits wide, thememory die is manufactured as x2 and encapsulated in a x4 package, thenthe maximum number of usable data pads is at most 2. All thecombinations shown in Table 1 have the property that the physicalpackage data width is greater than or equal to the memory die datawidth. However, the memory die data width can, in general, be greaterthan the package data width.

Therefore, the dynamic configurability of the memory device of thepresently described embodiments allows for its use in a package havingany suitable number of data pins. It is noted that there areconfigurations shown in Table 1 where the package has a greater numberof data pins than there are active data pads in the memory device. Inorder to make the characteristics of the memory device directlyavailable to the memory controller, the memory device includes one ormore registers readable by the memory controller that encode thosecharacteristics. In particular, the memory device includes an I/O WidthRegister that encodes the width of the Sin and Sout data ports on thedie and makes this width available to the memory controller. Otherembodiments may include the physical package width in this or anotherregister as well. The primary distinction between these two classes ofembodiments stems from the previously noted constraint found for examplein Table 1 that the physical package width is greater than or equal tothe memory die data width. If this constraint is present, then the I/OWidth Register need only encode the memory die data width. If theconstraint is not present then the I/O Width Register needs to eitherencode both the physical package data width and the memory die data withor the lesser of the two. Since it is undesirable to dedicate additionalpins on the package for the purpose of setting the number of input andoutput data pins that are currently enabled, the die includes a CurrentActive Width Register. The die is configured dynamically according tothe value stored in this register such that the number of input andoutput data pads that are enabled for use is equal to the stored valueor an appropriate alternative value indicative of the current activedata width. The remainder, if any, of the physical input and output datapads and their corresponding circuits are disabled. Based on physicallink widths of the PCB and/or system considerations, the memorycontroller will then load the Current Active Width Register with theappropriate data for disabling unused data pads and directing allcommunication (in and out of the serial memory device) onto theremaining enabled data pads.

FIG. 6 is a partial block diagram embodiment of a memory die havingconfigurable data widths. The arrangement of the circuit blocks are notintended to represent a physical layout or positioning of the blocks inthe manufactured die. This memory die can be used in the systems shownin FIGS. 3A and 3B. Memory die 500 is designed and manufactured as a x4die, and therefore has four data input pads 502 and four correspondingdata output pads 504. Each pairing of a data input pad 502 and a dataoutput pad 504 is coupled to a data I/O circuit block 506. Logically,the top-most data I/O circuit block 506 is the least significant, andthereby labeled “Data_(—)0”. The remaining data I/O circuit blocks 506are labeled in an order of increasing logical significance “Data_(—)1”,“Data_(—)2” and “Data_(—)3”. Each data I/O circuit block 506 is coupledto the memory core 508, which includes the memory array, control logic,and other circuits that are necessary for proper operation of the memorydie 500. Each data I/O circuit block 506 can pass input data through toits corresponding data output pad 504 and/or to the memory core 508.Read data from the memory core 508 can be provided to each data I/Ocircuit block 506 for output through the data output pads 504. Coupledto the memory core 508 are several registers, which include a I/O Width(I/O) register 510, an Current Active Width (CAW) register 512, anassigned device address (ADA) register 514, and broadcast address (BA)detector 516.

Typically the memory core 508 is organized as a very wide array with agreat many data lines internally. Also typically, the wide internal databus is coupled to a narrow I/O data path that couples the memory core tothe data pads. The coupling between the wide memory data path and thenarrow internal I/O data path is accomplished by the equivalent of acollection of bidirectional multiplexors that funnel bits to and fromthe narrow data path onto specific lines of the wide data path. Thereare several common mechanisms for implementing this multiplexingfunction that are well know to those skill in the art. In a previouslyconsidered memory device, the control of these multiplexors was derivedin part from the address of the memory core access, and typically thecolumn address in particular. However, in the serial memory device ofthe present invention, the control of these multiplexors is derivedadditionally from the contents of Current Active Width register. Therouting between the wide internal data path and the narrow I/O data pathto the I/O pads is thus dependent on the number of I/O pads currently inuse. The nature of this control is well know to those skilled in the artas it is analogous to the adjustment of the control of thosemultiplexors that is common when a single memory die design is able tobe fuse programmed to be one of any number of fixed width devices duringfunctional test or packaging. A analogous situation exists with regardsto the problem of capturing the control and address portions of incomingcommands. These portions, described subsequently in relation to FIG. 9,arrive on different data input pads according to the value stored in theCAW register. Consequently, the multiplexers that shunt incoming bitsinto the appropriate locations in registers that temporarily hold deviceaddresses, op codes and memory array addresses must all also becontrolled in part depending on the contents of the CAW register.

The I/O Width Register 510 is hardwired to store data indicating themaximum data width configuration of the memory die 500 and optionallythe number of package pins to which its data pads are physicallyconnected. Hardwiring includes setting a non-volatile data storage meansthat is sensed upon power up of the memory device 500. Such non-volatiledata storage means includes fuses that can broken electrically or bylasers, and anti-fuses which can be electrically blown to create anelectrically conductive link. Those of skill in the art will understandthat any suitable non-volatile programming technique can be used. TheCAW register 512 serves two purposes. First, when the desired data widthconfiguration is determined by the memory controller, a configurationcode is issued to all the memory devices in the system by the memorycontroller. This configuration code is loaded into the CAW register 512to enable only data I/O circuit blocks 506 that are to be used, therebysaving power. This configuration code is further used by the controllogic of the memory core 508, such as a command decoder, to ensureproper mapping of the received and provided data based on the currentactive data width configuration of the memory device 500. During initialpower up of the memory device 500, the default current active data widthconfiguration is set to the minimum possible setting, which is x1. In adefault x1 current active data width setting, only the data I/O circuitblock 506 corresponding to logical position Data_(—)0 is enabled.

The ADA register 514 stores an assigned device address issued by thememory controller, thereby allowing the memory device 500 to act oncommands specifically addressed to it. Accordingly, the sameconfiguration code can be issued to each memory device in the system byissuing commands addressed to each memory device. Such a globaloperation can be more efficiently done by broadcasting the configurationcode to all the memory devices, regardless of their assigned deviceaddress. As will be described later, the memory device 500 can be presetto recognize one address, referred to as a broadcast address, which willnever be assigned to any memory device but is recognized by all thememory devices. Optionally, the broadcast address can be dynamicallydetermined based on the number of memory devices in the system and thedevice addresses that have been assigned. Therefore, this broadcastaddress is stored in a register of BA detector 516 for comparison withthe address associated with an incoming command.

Accordingly, memory devices organized according to FIG. 6 can be used insystems such as the ones shown in FIGS. 3A and 3B. In some examples, allthe memory devices in the system are functionally identical, meaningthat they have the same package and memory device within it. However, amix of memory devices can be included in the system of FIGS. 3A and 3B.Though it is possible and desirable that all the memory devices in thesystem have the same physical package width and the dies have the samedata width, this is not necessarily the case. A collection of memorydevices can be placed in a system according to FIG. 3A or 3B even ifthey have different characteristics.

According to one embodiment, the system includes the ability to add orremove one or more memory devices during system build or in the field.FIG. 7 is a block diagram illustrating a dynamically adjustable systemembodiment. Adjustable system 600 includes a memory controller 602,fixed memory devices 604, 606, 608 and 610, expansion links 612, 614,616, 618 and 620, and expansion modules 622, 624 and 626. Fixed memorydevices 604, 606, 608 and 610 are serially connected to each other, tointervening expansion links, and to the memory controller 602. Eachexpansion link is a male, female or androgynous coupling means forreleasably receiving and retaining a module having a correspondingcoupling means. Each module includes at least one fixed memory device611 serially connected with the terminals of the expansion link. In thepresently shown example, expansion modules 622 and 626 each include fourmemory devices that are serially connected between input connectors andoutput connectors of the module coupling means. Module 624 includes twomemory devices serially connected between input connectors and outputconnectors of its module coupling means. Therefore, by inserting themodule into an expansion link, additional serially connected memorydevices can be dynamically inserted between fixed memory devices. Unusedexpansion links, such as expansion links 614 and 620 will have suitablejumpers 628 and 630 connected thereto for maintaining a continuousserial electrical connection of the chain.

The adjustable system 600 can include any suitable number of fixedmemory devices and expansion links, and the memory modules can includeany suitable number of serially connected memory devices. Therefore, theadjustable system 600 is fully expandable in memory capacity simply byadding new modules or replacing existing modules with larger capacitymodules, without impacting overall performance. There is no requirementto change the memory controller, since the same channel is beingpopulated with additional serially connected memory devices, and thoseskilled in the art will understand how to connect parallel controlsignals such as CE#, RST# and power supplies to the inserted modules.After insertion of the modules, or removal of modules, the memorycontroller may initiate automatic device ID generation for the new setof memory devices in the system 600.

In such an embodiment, there can be a mixing of memory devices in thesystem, where different memory devices may have different physicalpackage data widths and die data widths. Accordingly, a maximum activedata path width of the system 600 is the smallest of the link widths,package widths and die widths amongst all the memory devices. Beforenormal memory operations can begin, the maximum active data path widthof the system is determined. Once this maximum active data path width ofthe system is determined, then all the memory devices operate with acurrent active data width that is equal to or less than the maximum datawidth. The determination of the maximum data width of the system andsetting of the active data width is done by the memory controller. FIG.8A is a flow chart outlining a method for setting a current active datawidth of the memory devices of a system, according to a presentlydescribed embodiment. This method will be described with reference tothe example system shown in FIG. 8B.

The method of FIG. 8A is performed as part of a power up initializationroutine of the system of FIG. 8B. It is assumed that the memorycontroller 700 is configurable up to a x4 data width, and therefore hasfour data output ports electrically connected to four physical conductorlines 702 implemented on the PCB of the system. While not shown in FIG.8B, memory controller 700 has four data input ports connected to fourphysical conductor lines that are directly connected to the data outputports of the last memory device. Each memory package 704 and 706 has itsdata pins bonded or selectively coupled to the conductor lines 702 ofthe PCB. In order to simplify the schematic, the data return path fromthe last memory device to the memory controller 700 is omitted, as arethe control signals used by the memory devices. Memory package 704 hastwo input and output data pins while memory package 706 has four inputand output data pins. The memory device 708 is manufactured to be x4,and only has its first two input/output data pads bonded to the pins ofpackage 704. Memory device 710 is manufactured to be x1, and has itsinput/output data pad bonded to the top pin of package 706.

The method begins upon power up of the system, whereby all the memorydevices default to the x1 active data width configuration, and thememory controller defaults to output data in the x1 data configurationin step 750. In this configuration, it is assumed that the top-most pinis the logical Data_(—)0 position, which is used for the default activedata width configuration. In the x1 link width all the memory deviceswill receive data issued by the memory controller. The memory controllerwill then perform ID number generation at step 752 in accordance withthe techniques disclosed in the previously mentioned commonly owned U.S.patent applications directed to memory ID number generation. After theID numbers are assigned and stored into respective ADA registers 514 ofeach memory device, the memory controller will individually access theI/O Width Registers 510 of each memory device by issuing a correspondingcommand at step 754. The memory controller will then assemble all theI/O Width Register data and mathematically determine the smallest of thelink widths, package widths and die widths across all the memory devicesin the system at step 756. In the system of FIG. 8B for example, memorydevice 708 has an active data width range of two, and memory device 710has a maximum active data width of one. Since memory device 710 does nothave a second data pin, the common active data width is one.

The I/O Width Registers inform the memory controller of the PhysicalPackage Data Width and/or the Memory Die Data Port Width of each of theserial memory devices in the ring. If both are not provided, the lowerbound of the other can necessarily be deduced by convention from the onethat is provided. In order determine the Maximum Usable Data Path Width,the memory controller must also know the minimum link width around thesystem. The most straight forward way for it to comprehend this is tospecify that the link segments must be no narrower than the memorycontroller's data port width, which it intrinsically knows. Analternative is to require that all link segments be of the same widthand that the memory controller be able to determine the link with of thelink segment connected to its Sin input port by the placement of weak(i.e. large resistance) pullup or pulldown resistors on those inputsconnected to a link trace 406, and the opposite for those not. Bysensing the voltage on its inputs when the ring is disabled (via the CE#signal), the memory controller can thus determine the minimum link widtharound the ring and thereby compute the maximum usable data path widtharound the entire ring. Yet another alternative of many is to rely onthe convention that all link widths will be necessarily wider than thenarrowest serial memory device in the ring. With this assumption inplace, the memory controller can determine the maximum usuable data pathwidth solely on the Physical Package data Widths and/or the Memory DieData Port Widths of the devices in the ring.

At step 758 the memory controller 700 will apply a preferred operatingprofile to set the final active data path width for the system to besome value less than or equal to the Maximum Usable Data Path Width. Forexample, one operating profile can be for high performance, a second canbe for minimized power consumption, and a third can be a balancedperformance and power profile. In the high performance profile themaximum data width is selected. On the other hand, the minimized powerconsumption profile may dictate that the minimum data width (ie. x1) beselected. The balanced performance and power profile may be a valuebelow the maximum data width of the system. An adaptive profile wouldcause the active data path width to be changed during the course ofnormal operation or at transitions from one system-level power orperformance state to another, depending on specific performance, powerand thermal constraints or optimizations. For example, the active datawidth might be changed from a large value to a smaller one as part of ageneral throttling of the system as a result of thermal over-temperatureevent. Once the memory controller 700 or software running on the hostsystem 12 has determined the common active data width to be used, eachmemory device is accessed at step 760 to load its CAW register 512 withthe appropriate configuration code. This can be done by broadcastingcommand to load the CAW registers 512 of all the memory devices with thecommon active data width. This must be done with a broadcast command orsome other comparable mechanism that changes the active data path widthof all serial memory devices essentially simultaneously because the ringcannot operate properly, even temporarily, if any two adjacent deviceson the ring do not have the same view of the current active width of thelink connecting them. In the present example of FIG. 8B, the maximumusable data width of the system is x1, thus memory device 708 remains atthe default x1 data width while memory device 710 remains at the defaultx1 data width. In the example of FIG. 8B, step 758 is not required ifall the memory devices have a maximum data width of x1. Similarly, inthis case, step 760 is optional since all the serial memory devices arealready operating as x1 devices per step 750.

Now that all the memory devices have been configured to have thedetermined active data width, further initialization operations ornormal operations can proceed. It is beneficial to perform the method ofFIG. 8A prior to other initialization operations because subsequentoperations can be executed more quickly if the active data width is setto be greater than the default x1 configuration. A mix of memory deviceshaving different physical package and die pad data width configurationscan be used together in the same system. In the embodiment of FIG. 7,the method of FIG. 8A is performed upon power up each time afterexpansion modules are removed or added.

As previously mentioned, broadcasting is a technique for simplifying thedistribution of common commands to all the memory devices in a system.Without broadcasting, separate commands are issued to each memory deviceby device address. This requires more time and overhead in the memorycontroller, as it needs to keep track of which devices have already beenissued the command. If the memory controller cannot be interruptedsafely, then there may be memory devices that do not receive thecommand. In the systems of FIGS. 3A and 3B, any command packet issued bythe memory controller will propagate through all the memory devices, andonly the memory device having an assigned device address matching thedevice address in the command will act upon the command. All othermemory devices will ignore the command. In the presently discussedbroadcasting technique, the memory controller issues one command packetthat is acted upon by each memory device as it propagates through allthe memory devices. Therefore memory controller operations are greatlysimplified.

The command packet 800 has the structure illustrated in FIG. 9, andincludes three fields, two of which are optional depending on thespecific command being issued by the memory controller. The first field,being a mandatory field, is the command field 802. The first optionalfield is an address field 804, and the second optional field is a datafield 806.

The command field 802 includes two sub-fields, the first being a deviceaddress (DA) field 808 and the second being an op code field 810. Thedevice address field 808 can be any suitable number of bits in length,and is used for addressing each memory device in the system. Forexample, a device address field 808 of 1 byte (8 bits) in length issufficient for addressing up to 256 (2̂8) memory devices, however thedevice address field 808 can be any desired length. One address can bereserved for addressing all memory devices simultaneously, i.e. forbroadcasting an operation. In an alternate embodiment, the deviceaddress field 808 can include a device type field to indicate the typeof memory device the op code field 810 is directed to. For example, thedevice type field can designate a DRAM, SRAM or flash memories. The opcode field 810 can be any suitable number of bits in length to representthe commands for any suitable number of memory devices, and can includea bank address. For example, the flash memory command set will havedifferent commands than a DRAM command set in view of inherentdifferences, hence the op code field is assigned to functionsaccommodate all possible commands from both command sets if the systemincludes both types of memory devices. However, a preferred alternativefor dealing with different types of memories is to have the op codespace divided into two collections of commands: those commands relatedto ring operation and those related to memory array operations. Theformer set can be consistent across all memory types, but the secondgroup need not be. The semantics of the op codes in this group would bememory type specific. For example, a particular op code that meantprogram when issued to a Flash memory might mean refresh when presentedto a DRAM. Since the memory controller must know what kind of memory isat each assigned device address, it does not matter if these functionsshare the same op code. The address field 804 is used for providingeither a row address (Row Addr) or a column address (Col Addr) or a fulladdress of a memory array, depending on the type of operation specifiedby the op code. The data field 806 will include any suitable number ofbits of data to be written or programmed to the memory device.Therefore, the command packets 800 will vary in size since write datamay not be required for a particular operation and both addresses andwrite data may not be required for a particular operation.

FIG. 10 lists example command packets which can be used for operating aflash memory device having the organization shown in FIG. 4, for use inthe previously described systems of FIGS. 3A and 3B. The byte positionsin FIG. 10 correspond to the order they are serially received by thememory device. The command field 802 occupies the first and second bytepositions, which includes the device address (DA) as the first byte ofinformation and an op code corresponding to the operation as the secondbyte of information. The op code is represented as a hexadecimal value,and the “X” indicates that the last half four bits of the byte can beany value. In the particular case of the Flash op codes of FIG. 10, the4 unused bits represented by the “X”s in the second nibble of the opcode byte for some commands are the location of a bank address. In thisway, conceptually some commands are directed at the serial memorydevice, and some are directed at specific banks within that device. Thisstructuring of the op code space facilitated bank-to-bank parallelismand concurrency within a single serial memory device. The address field804 can include a three-byte row address (RA) occupying the third tofifth byte positions, but may be shortened for other commands to includea two-byte column address (CA) occupying only the third and fourth bytepositions. For commands including a two-byte column address, the datafield 806 will occupy the fifth byte position to the 2116^(th) byteposition or beyond, if the data should be that length. The data canoccupy an arbitrary number of byte positions.

Any command packet 800 issued by the memory controller is receivedserially by each memory device in the system, and only the memory devicehaving an assigned device address matching the DA sub-field 808 of thecommand field 802 will act upon the op code sub-field 810. The commandpacket is passed through the memory device and to the next memory devicein the chain. Since the op code is specific to a particular operation,the interface and control logic block 308 of the memory device 300 ofFIG. 4, will control the required circuits for latching address and/ordata information of the command packet. For example, if a page readcommand packet is received by the designated memory device, thedesignated memory device will decode the op code and control theappropriate circuits to latch the following three byte row address. Theexample command packets listed in FIG. 10 are directed to flash memoryoperations. A set of command packets for any other type of memory devicehaving different operations can follow the described command structure.If the DA sub-field 808 is n-bits in length, then up to 2̂n total deviceaddresses can be provided, thereby addressing up to 2̂n memory devices.In the presently described embodiments, (2̂n)−1 of the addresses areassigned to a corresponding number of memory devices, and one of theseaddresses is reserved as the broadcast address.

In FIG. 10, the “Operation Abort” command is shown to be directed to aspecific memory device. However this command can be broadcast to all thememory devices by setting the 1^(st) byte to hexadecimal address FFh. Inthe present example, it is assumed that address FFh is an unassigned DAreserved for broadcasting commands. The abort operation is analogous toa soft reset, in which all operations in progress are halted to returnthe memory device to a standby state. The “Write CAW Register” commandis shown as a broadcast command in that the device address in thiscommand in FIG. 10 is FFh. This command is used in the aforementionedmethod of FIG. 8A for loading the CAW register 512 with the selectedactive data width configuration code. Although not shown in FIG. 10,test commands for placing all the memory devices into preset test modescan also be broadcast.

In order for the memory devices of the systems shown in FIGS. 3A and 3Bto respond to the broadcast command, simple logic circuitry is used todetect the predetermined broadcast address (BA). FIG. 11 is a circuitschematic illustrating one possible circuit embodiment of device addresslogic within each memory device of the presently described embodiments.With reference to the memory device shown in FIG. 6, this logic would beimplemented within the memory core 508.

In FIG. 11, the device address logic 830 is responsible for generating amaster enable signal EN for enabling other logic and circuits of thememory device to act upon the received command packet in response toeither the designed device address or the broadcast address. Deviceaddress logic 830 includes the ADA register 514 for storing an assigneddevice address from the memory controller, XNOR logic 832, AND logic833, OR logic 834, and the BA detector 516. The XNOR logic 832 receivesall n-bits stored in the ADA register 514, and performs bit-by-bitcomparison with the n-bits of the device address DA[1:n] of the commandpacket. The bus DA[1:n] communicates the device address of the currentcommand once it has been entirely received. The amount of time needed toreceive the device address portion of the command depends on the widthof the field (1 byte in the example of FIG. 10), and the current activedata path width, as encoded in the CAW register. The device addressDA[1:n] is held temporarily in a register (not shown) at least until thecommand packet is entirely received. The XNOR logic 832 will generate nintermediate output signals corresponding to the comparison of the n-bitpositions of the device address DA[1:n] with those of the ADA register514. AND logic 833 receives all n intermediate output signals togenerate a single enable signal en1 at the high logic level if all bitpositions between the ADA Register 514 and DA[1:n] match. The broadcastaddress (BA) detector 516 receives the device address DA[1:n] andgenerates a single enable signal en2 at the high logic level if the BAmatches the predetermined BA set for all the memory devices in thesystem. OR logic 834 receives both en1 and en2 to generate a high logiclevel master enable signal EN when either en1 or en2 rises to the highlogic level. Therefore the memory device will respond to the commandwhen the command packet includes a matching device address or broadcastaddress. As previously noted, the broadcast address can be preset andfixed, or dynamically assigned by the memory controller.

FIG. 12 is a circuit schematic of BA detector 516 according to oneembodiment. In this embodiment, the broadcast address is preset andfixed and decoded by a decoder logic 836. In this example, the presetbroadcast address is a collection of logic “1” bits, which representsthe highest logical address. Therefore the decoder logic 836 isimplemented as a NAND logic gate having n-inputs, each receiving one bitposition of the device address DA[1:n]. Accordingly, en2 is at the lowlogic level if DA[1:n] are all logic “1” bits. the Those skilled in theart will understand that any decoder logic configuration can be usedbased on the pre-selected broadcast address, such that the enable signalen2 is driven to a logic level indicating a match between DA[1:n] andthat pre-selected broadcast address.

FIG. 13 is a circuit schematic of BA detector 516 according to anotherembodiment. In this embodiment, the broadcast address is dynamicallyassigned by the memory controller and stored in the BA register 838. Inthis embodiment, the memory controller will address each memory devicewith a command for loading BA register 838 with the selected broadcastaddress. This command can be similar to the “Write CAW Register” commandshown in FIG. 10. Once loaded, the n-bits of the BA register arecompared to the n-bits of the received device address DA[1:n] with XORlogic 840. If all the bit positions match, then XOR logic 840 generatesn intermediate output signals corresponding to the comparison of then-bit positions of the device address DA[1:n] with those of the BAregister 838. AND logic 842 receives all n intermediate output signalsto generate single enable signal en2 driven to the high logic level whenall the address bits of DA[1:n] match the corresponding bits of BAregister 838.

The previously shown embodiments of the device address logic 830 and BAdetector 516 are implemented with logic circuits that provide high logiclevel enable signals en1 and en2 when a matching device address orbroadcast address is received. In alternate embodiments, inverted logiccan be used such that enable signals en1 and en2 are driven to a lowlogic level when a matching device address or broadcast address isreceived.

Therefore, the systems of FIGS. 3A and 3B can be addressed with abroadcast operation before and after device addresses have beenassigned. The broadcast operation is initiated when the command packetis issued by the memory controller and completed when the memorycontroller receives its issued command packet from the last memorydevice in the system. FIG. 14 is a flow chart of a method for executinga broadcast operation in all the memory devices of the systems of FIGS.3A and 3B. The broadcast method of the system starts at step 850 whenthe memory controller issues a command packet that includes the presetor assigned broadcast address, referred simply as the broadcast addressfrom this point forward. The command packet is received by the firstmemory device in the system, referred to as memory device i, where i isan integer value greater than 0, at step 852. When received, deviceaddress logic such as device address logic 830 of FIG. 11 will match thebroadcast address in the command packet with the stored broadcastaddress, or it will decode the broadcast address to determine if is thevalid broadcast address.

Upon determining a valid or matching broadcast address, the memorydevice is enabled to perform the op code command of the command packetat step 854. At step 856 the command packet is passed to the subsequentdevice in the system, which may be a subsequent memory device or thememory controller. From step 858, the method loops back to step 852 whenthe subsequent device is another memory device. Parameter i isincremented at step 860 to indicate that steps 852, 854 and 856 areperformed by the next subsequent memory device in the system.Eventually, the method will proceed to step 862 from step 858 when thelast memory device in the system passes the command packet to the memorycontroller. At step 862 the memory controller receives the commandpacket it originally issued, and the broadcasting operation iseffectively ended since all the memory devices have received and actedupon the command packet. Therefore, all the memory devices will performthe operation with a single issued command from the memory controller.The steps of FIG. 14 are performed strictly sequentially in that it isnot the case that one step does not begin until after the previous stepis complete. For systems of FIGS. 3A and 3B, the arcs of FIG. 14indicate logical or conceptual sequence of events and not necessarilythe actual order of the events. Since the duration of each step can belonger than the gap between the initiation of subsequent steps,indicating that multiple steps can be occurring and they can even appearto happen out of order. For example, step 854 cannot begin until all ofthe op code bits of a command packet have been received. If the currentactive data path width is x1, this can be many clock cycles from thestart of the packet. However, forwarding the command packet to the nextdevice (step 856) begins almost immediately. In fact, with a narrowcurrent active width and a ring with a small number of serial memorydevices, in the beginning of the command packet can have gone all theway around the ring before the first device has received all of both ofthe device address and the op code.

In the systems of FIGS. 3A and 3B, the issuance of commands isaccompanied by the assertion of the command strobe input CSI. CSI isused for controlling the capturing of command packets appearing on theinput port Sin as they flow through the serial memory device to theoutput port Sout. and the assertion of CSI has a pulse durationcorresponding to the length of the command packet received. Hence theprotocol for issuing commands by the memory controller in the presentsystem embodiments is straightforward, since the memory controllerdesigner need only ensure that a CSI pulse is synchronized with thecommand packet that is issued. Some commands that are issued willinstruct the addressed memory device to provide output data. After apredetermined amount of time, the output data will be ready for output,meaning that the read data has been loaded into a read data registerduring internal memory read operations. The serial memory device is saidto be selected and ready to output data. The read protocol for executinga read operation in the presently described system embodiments specifiesthat a data strobe input DSI pulse is issued after the CSI pulse withthe read command packet. DSI is used for enabling the output circuitsfor the Sout output port, such as data I/O circuit block 506 of FIG. 6,to output read data, and has a pulse duration corresponding to thelength of the read data being requested. More specifically, the DSIpulse will enable data from the read data register to be clocked outthrough the Sout output port via data I/O circuit block 506. For eachdevice, CSO and DSO are time shifted versions of CSI and DSI, providedso that the next device in the ring can capture commands and dataappropriately.

FIGS. 15 and 16 are sequence diagrams illustrating valid read operationsperformed by a memory device in response to control signals CSI, DSI anda read command packet. In FIG. 15, CSI is pulsed for the duration of anissued read command packet. The incoming Read command is sent onto theSout port at the same time as it is being interpreted. As an optionaloptimization, once the read command is recognized as being addressedspecifically to the present device (i.e. DA byte=ADA register)forwarding of the command to the next device in the ring can stop at anylegal command length boundary. The read command packet can include anyof the commands listed in FIG. 10 where some type of information is tobe read out from the memory device. If the read command packet isaddressed to the last memory device in the system, then the CSI pulseand the read command packet are passed through each intervening memorydevice, and is then acted upon by the last memory device. After aminimum time period necessary for the memory device to prepare the readdata has passed, the memory controller can issue a DSI pulse. This pulseis passed through the intervening memory devices, and is only acted uponby the selected last memory device. Data is then clocked out on the Soutoutput of the selected last memory device for the duration of the DSIpulse, aligned with a corresponding pulse of DSO. It is noted that thedata is provided after a delay relative to the rising edge of DSI. Inthe presently described embodiments, this delay is a single clock cycle,but can be any number of clock cycles depending on the design andconfiguration of the memory device. For both the forwarding of thecommand and the output data, the corresponding CSO and DSO strobes areoutput concurrently with the data on Sout.

In FIG. 16, CSI is pulsed for the duration of an issued read commandpacket, where the read command corresponds to a burst read command forexample. After a minimum time period necessary for the memory device toprepare the read data has passed, the memory controller can issue afirst DSI pulse to enable the selected memory device to output a firstportion of the read data. The first DSI pulse is de-asserted by drivingit to the low logic level to temporarily halt, or pause data output.This may be done for example, in order to accommodate other systemoperations. Then the memory controller can issue a second DSI pulse toenable the selected memory device to output a second portion of the readdata, which can be the remaining portion of the data stored in theserial data register 902. This second DSI pulse can be de-asserted, anda third DSI pulse can be issued to complete the data output for theremaining data. According to the presently described embodiment, outputdata on the Sout output of a selected memory device is clocked out inresponse to a received DSI strobe only when the previous CSI strobe isassociated with a read command for the selected memory device, asindicated by a matching device address and an appropriate op code byte.In both the sequences of FIGS. 15 and 16, at least one DSI pulseimmediately follows a CSI pulse for a read command. If DSI is assertedby the memory controller after any non-read command packet addressed tothe present serial memory device or any command packet address toanother serial memory device, output circuits for providing read datafrom the memory of the selected memory device are inhibited fromproviding any read data. Since read data is provided in response to DSI,the memory devices can ignore any DSI assertion that follows an assertedCSI for a non-read command packet to the present serial memory device.In alternate embodiments, the rules for what constitute a valid DSIinput can be different. For example, if the command protocol allows anon-read command to one device to not disturb the another device that isselected for data output, then a DSI pulse can be directed to anotherserial memory device on the ring that is potentially either before orafter it on the ring. In this case, the bits received on the Sin portduring such a DSI pulse need to be copied to the Sout port so as to notinterfere with communication between the memory controller and otherserial memory devices. It will be understood by those skilled in the artthat a variety of command protocols are possible with different rulesfor ignoring or forwarding CSI and DSI pulse and the contents of Sin.

FIG. 17 is a circuit schematic showing data output control logic anddata output circuits which can be implemented in the memory device 500of FIG. 6. The data output control logic is an example illustrating howthe data output circuit can be disabled, or inhibited, from providinginternal read data. Those skilled in the art will understand that otherlogic structures can be developed for achieving the same desired result.FIG. 17 shows a data output selector 900, a serial data register 902, aread data output controller 904, and an ID generation block 905. In thepresently described embodiment, the data output selector 900 isimplemented in each data I/O circuit block 506 of FIG. 6, and includes amultiplexor 906 that receives internal read data RD_DATA received fromthe serial data register 902, and pass through data P_DATA from an Sininput port of the memory device via latch 907. Multiplexor 906 will passeither P_DATA or RD_DATA in response to data selection signal DSelect.The selected output is then driven by output driver 908 onto output portSout. Pass through data P_DATA is a serial stream of data that isreceived by other logic circuits, which are not shown to simplify theschematic. These other circuits will pass write data to the memory arrayand command data to the command decoder of the memory device. RD_data isprovided from multiplexor 909, which passes data from either serial dataregister 902 or data from ID generation block 905 in response toregister select signal Rselect. Register select signal Rselect isprovided from the command decoder in response to a command for reading aparticular register. ID generation block 905 includes the registersdiscussed in FIGS. 6, 11,12 and 13, other registers for providing statusinformation, as well as additional logic circuits for providing anupdated ID number. For example, when the memory device is assigned an IDnumber, ID generation block 905 generates an updated ID number that ispassed to multiplexor 909 during the ID generation phase of operation.This updated ID number is then passed through multiplexors 909 and 906and onto Sout for the next memory device.

The serial data register 902 can be part of each data I/O circuit block506 or the memory core 508 of FIG. 6, but in the presently describedembodiment the serial data register 902 is a part of the memory core508. Serial data register 902 can be any type of data register thatoutputs data serially in response to transitions of an input clock. Itcan be loaded with data read from the memory array M_DATA eitherserially or in parallel. Persons of skill in the art will be familiarwith the different types of serial registers that are known in the art,which can be used in FIG. 17.

The read data output controller 904 is responsible for controlling theserial data register 902 during valid and invalid sequences of the CSIand DSI control signals. The read data output controller 904 includes alatch 910, and AND logic circuits 912, 914 and 916. Latch 910 receivessignal READ which is latched in response to a high logic level of CSI.It is noted that both latch 907 and 910 are level sensitive latches. TheREAD signal is set to a high logic level when a received command isaddressed to the present serial memory device and corresponds to anytype of read operation, but is set to a low logic level when thereceived command either is addressed to another serial memory device oris not any of the recognized read operations. Since the command decoderwill decode the received command for an addressed memory device toperform read and write operations, the generation of READ should beeasily achieved with well known logic. The output of latch 910 isreceived by a first input of AND logic circuit 912, which receives aninternal clock signal CLK at its second input. The internal clock signalCLK can be synthesized within the memory device in response to anexternal clock, or a buffered version of an external clock. AND logiccircuit 912 will either pass CLK or a low logic level output dependingon the output of latch 910.

CLK is used by other internal circuits of the memory device, includingthe serial data register 902 for clocking out loaded data. AND logiccircuit 914 has one input for receiving the output of AND logic circuit912, and another input for receiving DSI. Therefore, when AND logiccircuit 912 passes CLK, CLK is passed to the serial data register 902when DSI is at the high logic level. Otherwise, the clock input ofserial data register 902 remains at the low logic level. DSI is furtherused to control multiplexor 906. AND logic circuit 916 has one input forreceiving DSI and another input for receiving an enable signal EN. Inthe presently described embodiment, enable signal EN is provided bydevice address logic 830 shown in FIG. 11, and is at the high logiclevel when either a broadcast address or matching device address isreceived by the memory device. In the presently described embodiment,AND logic circuit 916 will drive its output data selection signalDselect to a high logic level when both DSI and EN are at the high logiclevel. Under these conditions, DSI has been asserted and the deviceaddress in the command packet matches that of the memory device.Accordingly, Dselect will control multiplexor 906 to pass RD_DATA.Otherwise, when DSI is not asserted and the memory device is not theaddressed one, then multiplexor 906 is controlled to pass P_DATA.

The operation of the circuits of FIG. 17 is briefly described withreference to the sequence diagram of FIG. 15 to illustrate its operationduring a valid assertion of DSI. First CSI is asserted by driving it tothe high logic level, and a read command packet is received at the Sininput of the memory device. It is assumed that the command packetaddresses the memory device to set EN to the high logic level, and thememory device performs internal read operations to load the serial dataregister 902 with read data M_DATA from the memory. Since the commandpacket is a read related command, signal READ is at the high logiclevel. With CSI at the high logic level, CLK is passed to AND logiccircuit 914 but prevented from being coupled to serial data register902. Later in time, DSI is asserted by driving it to the high logiclevel. As soon as DSI goes to the high logic level, DSelect will controlmultiplexor 906 to pass RD_DATA. With DSI at the high logic level, CLKis coupled to the serial data register 902 to clock out the stored datathrough multiplexor 906 to output driver 908. Accordingly, the dataprovided in the Sout output port is valid read data from the memorydevice. In the situation of FIG. 16 where DSI drops to the low logiclevel, and is then asserted again later, it is noted that AND logiccircuit 914 will decouple the output of AND logic circuit 912 from theserial data register 902 when DSI drops to the low logic level. When DSIrises again, CLK is coupled to the serial data register 902 to continueserial data output.

The operation of the circuits of FIG. 17 is briefly described withreference to the sequence diagrams of FIGS. 18 to 20 to illustrate itsoperation during invalid assertions of DSI. In FIG. 18, CSI is assertedin association with a command packet that is not a read related command,where the non-read command corresponds to a write command for example,and is addressed to the memory device. Hence signal READ is at the lowlogic level, which is latched when CSI is at the high logic level.Therefore AND logic circuit 912 will inhibit CLK from being passed toAND logic circuit 914. When DSI is asserted later, AND logic circuit 914will pass a static low logic signal to serial data register 902.Accordingly, DSI will have no effect on the serial data register 902since CLK has been inhibited by AND logic circuit 912. Therefore RD_DATAwill correspond to the data being held in the first register circuit ofserial data register 902 coupled directly to multiplexor 906. Byinhibiting DSI from the serial data register 902, any potential randomdata in the serial data register 902 is prevented from being asserted onthe Sout output port. In one embodiment, the Sout output port isstatically held at one logic level for the duration of the DSI pulse.Therefore, the memory controller can recognize a continuous sequence of“0” or “1” logic states as being the result of an invalid operation,that being the assertion of DSI after a non-read based command. It isnoted that the addressed memory device will perform the non-readoperation, such as a write operation for example.

In FIG. 19, CSI is first asserted in association with a read commandpacket addressed to the memory device. Accordingly, CLK is coupled toAND logic circuit 914 in the same manner as previously described for thesequence diagram of FIG. 15. Meanwhile, the memory device willinternally perform the read operation and load the serial data register902 with M_DATA. CSI is asserted again in association with an issuednon-read command packet, such as a write command packet for example,addressed to the same memory device. Latch 910 will latch READ at thelow logic level, resulting in AND logic circuit 912 inhibiting CLK frombeing coupled to AND logic circuit 914. When DSI is later asserted,DSelect will control multiplexor 906 to pass RD_DATA, but DSI AND logiccircuit 914 does not receive CLK. Therefore serial data register 902 isdisabled and does not output its contents, except for the bit of datastored in the first register circuit. In the presently describedembodiment, it does not matter that the non-read command packet wasaddressed to a different memory device because the command decoder logiccan remain active for setting READ to the high or logic level. In such acase the previously addressed memory device would not respond to thecommand and its multiplexor 906 is set to pass P_DATA even when DSI isasserted because EN is set to the low logic level. In the memory deviceaddressed by the non-read command, its multiplexor 906 is set to passRD_DATA, but its serial data register 902 will be disabled in the mannerdescribed for the situation described for FIG. 18.

In FIG. 20, CSI is first asserted in association with a read commandpacket addressed to the memory device, where the read commandcorresponds to a burst read command for example. Accordingly, CLK iscoupled to AND logic circuit 914 in the same manner as previouslydescribed for the sequence diagram of FIG. 15. DSI is asserted a firsttime after the initial CSI strobe with the burst read command.Multiplexor 906 is controlled to pass RD_DATA and serial data register902 receives CLK to clock out its stored data through to the Sout outputport. In the present burst read example, DSI is de-asserted by drivingit to the low logic level to temporarily halt, or pause, data output.This situation is the same as the burst read operation shown in FIG. 16.However, instead of a second asserted DSI pulse, CSI is asserted afterDSI is de-asserted in association with a non-read command packet, wherethe command corresponds to a write operation for example. This non-readcommand packet can be addressed to any memory device. In all the memorydevices, latch 910 will output a low logic level to AND logic circuit912, thereby inhibiting CLK from being coupled to AND logic circuit 914,and in turn inhibiting CLK from being coupled to serial data register902. Therefore, any assertion of DSI following the assertion of CSI forthe non-read command packet is ignored by all the memory devices. TheSout output port of the addressed memory device will statically providedata having one logic level for the duration of the DSI pulse.

The valid and invalid issuance of the data output control signal, suchas DSI in the presently described embodiments of the system of FIGS. 3Aand 3B, can be summarized into a data output inhibit algorithmembodiment followed by each memory device. More specifically, the dataoutput inhibit algorithm is followed by the command decoder of eachmemory device. FIG. 21 is a flow chart summarizing the data outputinhibit algorithm according to a presently described embodiment.

The method begins at step 950 when a first control signal being either aDSI or a CSI is received by the memory device. If at step 952 thereceived control signal is a CSI signal with a corresponding command,then if the command is addressed to the present serial memory device asdetermined at step 953, then the method proceeds to step 954. From step954, if the CMD is a non-read operation, then the method proceeds tostep 956 to perform the non-read operation. Then the memory devicereturns to step 950 to wait for the next control signal. Returning tostep 954, if the received CMD was a read related command, then the readoperation is performed at step 958 to prepare the read data for output.The method then returns to step 950 when the next control signal isreceived. If the next control signal is an asserted DSI, the methodproceeds from step 952 to step 962 via step 961 if the serial memorydevice was selected by the previous command. Step 961 verifies that theprevious device address of the command matches the assigned deviceaddress. In that case, if the previously received CMD corresponded to aread command, then the read data is output at step 964 in response tothe received DSI. If the next control signal is another DSI, then themethod returns to step 964 to output further data. This particular loopmay continue for any number of consecutive asserted DSI control signals,resulting in valid data output.

Returning to the scenario where the read command is performed at step958, and another CSI is received with a corresponding non-read relatedcommand, the method proceeds from step 952 to 962, where it isdetermined that the command is non-read related. Then the data outputoperation is aborted at step 966. Hence any asserted DSI received afterCSI corresponding to a non-read related command will result in anaborted data output operation. Accordingly, if the memory controllerissues invalid read commands by asserting the DSI control pulse, astatic logic “0” or “1” data stream is returned to it. Hence the memorycontroller can recognize this data pattern as a result of an invalidcommand, and no data is provided to the host system. In the situation ofFIG. 19, the memory controller can re-issue the first read commandpacket since the original read operation was aborted with the issuanceof the non-read command packet before assertion of DSI.

The previously described system with memory devices operates at greaterspeeds than parallel multi-drop systems of the prior art, therebyproviding superior performance. The performance of each memory device,and of the system in turn, is further improved as more serial input andoutput data ports are provided. If the memory devices employ thepreviously described configurable data width embodiments, each memorydevice is dynamically configurable to operate with a minimal activenumber of data pads to reduce power consumption. The memory devices areconfigurable through the issuance of a single command propagatedserially to all the memory devices from the memory controller in abroadcast operation. Robust operation of the system is ensured byimplementing the data output inhibit algorithm, which prevents validdata from being provided to the memory controller, when the memorycontroller improperly issues a read output control signal. Theseaforementioned embodiments can be implemented independently of eachother, or in combination with each other in a memory device or memorycontroller of a system.

Certain adaptations and modifications of the described embodiments canbe made. Therefore, the above discussed embodiments are considered to beillustrative and not restrictive.

What is claimed is:
 1. A system comprising: a memory controller having afirst number of output ports, the memory controller providing a commandto access maximum data width configuration data from one output port ofthe first number of output ports; and, a memory device having aninput/output register for storing the maximum data width configurationdata, a second number of data input pads and the second number of dataoutput pads, the memory device receiving the command at one data inputpad of the second number of data input pads and providing the maximumdata width configuration data from one data output pad of the secondnumber of data output pads.